For the past several decades, the scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, leading to the fabrication of products with increased processing capacity. The drive for ever-more processing capacity, however, is not without issue. The necessity to optimize the performance and energy consumption of each device becomes increasingly significant.
In the manufacture of IC devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, Tri-Gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. On bulk silicon substrates, however, the fabrication process for tri-gate transistors often encounters problems when aligning the bottom of the metal gate electrode with the source and drain extension tips at the bottom of the transistor body (i.e., the “fin”). When the tri-gate transistor is formed on a bulk substrate, proper alignment is needed for optimal gate control and to reduce short-channel effects. For instance, if the source and drain extension tips are deeper than the metal gate electrode, punch-through may occur. Alternately, if the metal gate electrode is deeper than the source and drain extension tips, the result may be an unwanted gate capacitance parasitic. Many different techniques have been attempted to reduce leakage of transistors. However, significant improvements are still needed in the area of leakage suppression.
As the size of transistors in ICs continues to decrease, the power supply voltage to the transistors must also decrease. As the power supply voltage decreases, the threshold voltage of the transistors in the ICs must also decrease. Lower threshold voltages are difficult to obtain in conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) because, as the threshold voltage is reduced, the ratio of ON-current to OFF-current (Ion/Ioff) also decreases. The ON-current refers to the current through a MOSFET when a gate voltage applied is above the threshold voltage and coupled be as high as equal to the supply voltage, and the OFF-current refers to current through a MOSFET when a gate voltage applied is below the threshold voltage and equals zero.
Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper sub-threshold slope. The current TFET devices suffer from lower currents than Si-MOSFETs at the same technology node and from a parasitic source to drain tunneling leakage current during OFF-current i.e., a reduced on/off ratio.